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ITF87052SVT
TM
Data Sheet
July 2000
File Number
4800.4
3A, 20V, 0.115 Ohm, P-Channel, 2.5V Specified Power MOSFET Packaging
TSOP-6
Features
* Ultra Low On-Resistance - rDS(ON) = 0.115, VGS = -4.5V - rDS(ON) = 0.120, VGS = -4.0V - rDS(ON) = 0.190, VGS = -2.5V * * * * 2.5 V Gate Drive Capability Small Profile Package Gate to Source Protection Diode Simulation Models - Temperature Compensated PSPICE(R) and SABERTM Electrical Models - Spice and SABER Thermal Impedance Models - www.intersil.com
4 1 2 3
Symbol
* Peak Current vs Pulse Width Curve * Transient Thermal Impedance Curve vs Board Mounting Area
DRAIN(1) DRAIN(2)
DRAIN(6) DRAIN(5)
* Switching Time vs RGS Curves
Ordering Information
PART NUMBER PACKAGE TSOP-6 (SC-95) 052 BRAND ITF87052SVT
GATE(3)
SOURCE(4)
NOTE: When ordering, use the entire part number. ITF87052SVT is available only in tape and reel.
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified ITF87052SVT -20 -20 -12/+6 3.0 3.0 1.5 1.5 Figure 4 2.0 16 -55 to 150 300 260 UNITS V V V A A A A W mW/oC oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA = 25oC, VGS = -4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 25oC, VGS = -4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 100oC, VGS = -4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 100oC, VGS = -2.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: 1. TJ = 25oC to 125oC. 2. 62.5oC/W measured using FR-4 board with 0.40 in2 (258.1 mm2) copper pad at 2 second.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. SABERTM is a trademark of Analogy Inc. PSPICE(R) is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
ITF87052SVT
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS(TH) rDS(ON) VGS = VDS, ID = 250A Figure 10 ID = 3.0A, VGS = -4.5V Figures 8, 9 ID = 1.5A, VGS = -4.0V Figure 8 ID = 1.5A, VGS = -2.5V Figure 8 THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RJA Pad Area = 0.40 in2 (258.1 mm2) (Note 2) Pad Area = 0.013 in2 (8.6 mm2) Figure 20 Pad Area = 0.009 in2 (5.8 mm2) Figure 20 SWITCHING SPECIFICATIONS (VGS = -2.5V) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time td(ON) tr td(OFF) tf VDD = -10V, ID = 1.5A VGS = -2.5V, RGS = 22 Figures 14, 18, 19 320 1200 650 820 ns ns ns ns 62.5 202 210
oC/W oC/W oC/W
TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
BVDSS IDSS IGSS
ID = 250A, VGS = 0V Figure 11 VDS = -20V, VGS = 0V VGS = 12V
-20 -
-
-10 10
V A A
-0.5 -
0.080 0.086 0.130
-1.5 0.115 0.120 0.190
V
SWITCHING SPECIFICATIONS (VGS = -4.5V) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at -2V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = -10V, VGS = 0V, f = 1MHz Figure 12 540 200 120 pF pF pF Qg(TOT) Qg(-2) Qg(TH) Qgs Qgd VGS = 0V to -4.5V VGS = 0V to -2V VGS = 0V to -0.5V VDD = -10V, ID = 3.0A, Ig(REF) = 1.0mA Figures 13, 16, 17 8 3 0.3 1 2.5 nC nC nC nC nC td(ON) tr td(OFF) tf VDD = -10V, ID = 3.0A VGS = -4.5V, RGS = 19 Figures 15, 18, 19 130 540 800 860 ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = -3.0A ISD = -3.0A, dISD/dt = 10A/s ISD = -3.0A, dISD/dt = 10A/s TEST CONDITIONS MIN TYP -0.82 30 2 MAX UNITS V ns nC
2
ITF87052SVT Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0
ID, DRAIN CURRENT (A)
-4
-3
0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
VGS = -4.5V, RJA = 62.5oC/W
-2
-1 VGS = -2.5V, RJA = 210oC/W 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
3 1
THERMAL IMPEDANCE ZJA, NORMALIZED
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM
RJA = 62.5oC/W
0.1
0.01
t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 101 102 103
SINGLE PULSE 0.001 10-5 10-4 10-3
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-300
IDM, PEAK CURRENT (A)
RJA = 62.5oC/W
TC = 25oC
-100
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25
VGS = -4.5V
150 - TA 125
-10
VGS = -2.5V
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103
FIGURE 4. PEAK CURRENT CAPABILITY
3
ITF87052SVT Typical Performance Curves
-100
(Continued)
-10
100s
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
-8
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V TJ = -55oC
-10 1ms
-6 TJ = 150oC -4 TJ = 25oC
-1
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TA = 25oC
10ms
-2
RJA = 62.5oC/W -40
-0.1 -1 -10 VDS, DRAIN TO SOURCE VOLTAGE (V)
0 -1.0 -1.5 -2.0 -2.5 VGS, GATE TO SOURCE VOLTAGE (V) -3.0
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. TRANSFER CHARACTERISTICS
-10
TA = 25oC
250
VGS = -3V
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m)
ID, DRAIN CURRENT (A)
-8 VGS = -4.5V -6 VGS = -2.5V
ID = -1.5A 200 ID = -3A 150
-4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
VGS = -2V
100
-2
VGS = -1.5V
0 0 -0.5 -1.0 -1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) -2.0
50 -1 -2 -3 -4 -5 VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
1.6
1.4
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = -250A
NORMALIZED GATE THRESHOLD VOLTAGE
160
1.4
1.2
1.2
1.0
1.0 VGS = -4.5V, ID = -3A 0.8
0.8
0.6
0.6 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
4
ITF87052SVT Typical Performance Curves
1.10
(Continued)
1000
NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
ID = -250A 1.05
CISS = CGS + CGD
C, CAPACITANCE (pF)
1.00
COSS CDS + CGD
0.95
VGS = 0V, f = 1MHz
0.90 -80 -40 0 40 80 120 160
CRSS = CGD
-1 -10 -20
100 -0.1 VDS , DRAIN TO SOURCE VOLTAGE (V)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-5
VGS , GATE TO SOURCE VOLTAGE (V)
VDD = -10V -4
SWITCHING TIME (ns)
1500 VGS = -2.5V, VDD = -10V, ID = -1.5A 1200 tf tr
-3
900
-2 WAVEFORMS IN DESCENDING ORDER: ID = -3A ID = -1.5A 0 2 4 Qg, GATE CHARGE (nC) 6 8
600
td(OFF)
-1
300
td(ON)
0
0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE ()
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
1250 VGS = -4.5V, VDD = -10V, ID = -3A 1000
td(OFF)
SWITCHING TIME (ns)
tf
750 tr 500
250
td(ON)
0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
ITF87052SVT Test Circuits and Waveforms
Qgs RL 0 VGS= -0.5V VGS VDD
+
VDS
Qgd
VDS
Qg(TH)
-VGS Qg(-2) VDD Qg(TOT) 0 Ig(REF)
VGS= -2V
DUT Ig(REF)
VGS= -4.5V
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
tON td(ON) RL VDS VGS +
tOFF td(OFF) tr tf 10% 10%
0
0V RGS -VGS DUT 0
VDS
90%
90%
10% 50% VGS PULSE WIDTH 90% 50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T JM - T A ) P DM = -----------------------------Z JA
1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the
(EQ. 1)
In using surface mount devices such as the TSOP-6 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 6
ITF87052SVT
necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads.
R JA = 120.6 - 18.9 x
Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
220 RJA = 120.6 - 18.9*ln(AREA) 200 RJA (oC/W) 180 164.0oC/W - 0.1in2 160 140 120 0.01 0.1 AREA, TOP COPPER AREA (in2) 1.0 194.4oC/W - 0.02in2
ln ( Area )
(EQ. 2)
The transient thermal impedance (ZJA) is also affected by varied top copper board area. Figure 21 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas.
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
200 160 120 80 40 0
IMPEDANCE (oC/W)
ZJA, THERMAL
COPPER BOARD AREA - DESCENDING ORDER 0.02 in2 0.05 in2 0.10 in2 0.25 in2 0.40 in2
10-1
100
101 t, RECTANGULAR PULSE DURATION (s)
102
103
FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA
7
ITF87052SVT PSPICE Electrical Model
.SUBCKT ITF87052SVT 2 1 3 ;
CA 12 8 9.3e-10 CB 15 14 9.7e-10 CIN 6 8 4.5e-10
ESG LDRAIN + 5 RLDRAIN EBREAK ESLC 50 DBODY + 17 18 DRAIN 2 RSLC1 51
REV January 2000
RSLC2
DPLCAP EVTHRES + 19 8 6
LGATE
EVTEMP RGATE 9
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 3.6e-9 LSOURCE 3 7 4.3e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
GATE 1 RLGATE
-
20 DESD1 91 DESD2
18 + 22
CIN
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1e-3 RGATE 9 20 650 RLDRAIN 2 5 10 RLGATE 1 9 36 RLSOURCE 3 7 43 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 4.8e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*32),2.1))} .MODEL DBODYMOD D (IS = 2.4e-11 IKF = 0.06 RS = 1.7e-2 TRS1 = 1.7e-3 TRS2 = 2e-6 CJO = 2e-10 TT = 5.1e-9 M = 0.27) .MODEL DBREAKMOD D (RS = 4e-1 TRS1 = 1e-3 TRS2 = 2e-6) .MODEL DESD1MOD D (BV = 10.8 TBV1 = -1.9e-3 N = 11 RS = 450) .MODEL DESD2MOD D (BV = 10.8 TBV1 = -1.9e-3 N = 11 RS = 450) .MODEL DPLCAPMOD D (CJO = 2.2e-10 IS = 1e-30 N = 10 M = 0.31 VJ = 0.45) .MODEL MMEDMOD PMOS (VTO = -0.95 KP = 1.7 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 650 RS = 0.1) .MODEL MSTROMOD PMOS (VTO = -1.10 KP = 9.7 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD PMOS (VTO = -0.75 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 6500 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 7.2e-4 TC2 = -5e-7) .MODEL RDRAINMOD RES (TC1 = 1.7e-1 TC2 = 1e-5) .MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RSOURCEMOD RES (TC1 = -1e-4 TC2 = 9e-6) .MODEL RVTHRESMOD RES (TC1 = 1.5e-3 TC2 = 3e-6) .MODEL RVTEMPMOD RES (TC1 = 0 TC2 = 2e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = 2.5 VOFF= 1.5) VON = 1.5 VOFF= 2.5) VON = 0.75 VOFF= -0.5) VON = -0.5 VOFF= 0.75)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
-
EBREAK 5 11 17 18 -27.08 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1
5 51
+
DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 6 DPLCAPMOD
10
-
8 6
-
RDRAIN 21 16 MWEAK MMED MSTRO 8 RSOURCE DBREAK 11
LSOURCE 7 RLSOURCE SOURCE 3
RBREAK 18 RVTEMP 19
VBAT +
8 22 RVTHRES
ITF87052SVT SABER Electrical Model
REV January 2000 template ITF87052SVT n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.4e-11, ikf = 0.06, cjo = 2e-10, tt = 5.1e-9, m = 0.27, rs = 1.7e-2, trs1 = 1.7e-3, trs2 = 2e-6) dp..model dbreakmod = (rs = 4e-1, trs1 = 1e-3, trs2 = 2e-6) dp..model desd1mod = (bv = 10.8, tbv1 = -1.9e-3, nl = 11, rs = 450) dp..model desd2mod = (bv = 10.8, tbv1 = -1.9e-3, nl = 11, rs = 450) dp..model dplcapmod = (cjo = 2.2e-10, isl = 10e-30, nl = 10, m = 0.31, vj = 0.45) m..model mmedmod = (type=_p, vto = -0.95, kp = 1.7, is = 1e-30, tox = 1, rs = 0.1) m..model mstrongmod = (type=_p, vto = -1.10, kp = 9.7, is = 1e-30, tox = 1) m..model mweakmod = (type=_p, vto = -0.75, kp = 0.06, is = 1e-30, tox = 1, rs = 0.1) ESG sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 2.5, voff = 1.5) 5 -8+ sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 1.5, voff = 2.5) 6 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.75, voff = -0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.75) 10 c.ca n12 n8 = 9.3e-10 c.cb n15 n14 = 9.7e-10 c.cin n6 n8 = 4.5e-10 dp.dbody n5 n7 = model=dbodymod dp.dbreak n7 n11 = model=dbreakmod dp.desd1 n91 n9 = model=desd1mod dp.desd2 n91 n7 = model=desd2mod dp.dplcap n10 n6 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 3.6e-9 l.lsource n3 n7 = 4.3e-9
GATE 1 RLGATE 91 DESD2 DPLCAP EVTHRES + 19 8 6 MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A S2A RBREAK 13 8 S1B 13 + EGS 6 8 EDS 14 13 S2B CB + 5 8 14 IT 15 17 18 RVTEMP 19 7 SOURCE 3 RSLC1 51 RSLC2 ISCL 50 RDRAIN 16 21 MWEAK MMED DBODY DBREAK
LDRAIN DRAIN 2 RLDRAIN
+ EBREAK 17 18
-
11
LGATE RGATE 9
EVTEMP
-
20 DESD1
18 + 22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 7.2e-4, tc2 = -5e-7 res.rdrain n50 n16 = 1e-3, tc1 = 1.7e-1, tc2 = 1e-5 res.rgate n9 n20 = 650 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 36 res.rlsource n3 n7 = 43 res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 4.8e-2, tc1 = -1e-4, tc2 = 9e-6 res.rvtemp n18 n19 = 1, tc1 = 0, tc2 = 2e-6 res.rvthres n22 n8 = 1, tc1 = 1.5e-3, tc2 = 3e-6 spe.ebreak n5 n11 n17 n18 = -27.08 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n5 n10 n8 n6 = 1 spe.evtemp n6 n20 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1
12 CA
VBAT +
-
-
8 RVTHRES
22
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/32))** 2.1)) } }
9
ITF87052SVT SPICE Thermal Model
REV January 2000 ITF87052SVT Copper Area = 0.02 in2 CTHERM1 th 8 1.1e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 7.0e-3 CTHERM4 6 5 9.0e-3 CTHERM5 5 4 1.1e-2 CTHERM6 4 3 4.0e-2 CTHERM7 3 2 3.0e-1 CTHERM8 2 tl 1.5 RTHERM1 th 8 2.5e-1 RTHERM2 8 7 6.0e-1 RTHERM3 7 6 1.25 RTHERM4 6 5 8 RTHERM5 5 4 10 RTHERM6 4 3 43 RTHERM7 3 2 48 RTHERM8 2 tl 50
th JUNCTION
RTHERM1 8
CTHERM1
RTHERM2 7
CTHERM2
RTHERM3 6
CTHERM3
RTHERM4
CTHERM4 5
SABER Thermal Model
Copper Area = 0.02 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 1.1e-3 ctherm.ctherm2 8 7 = 5.0e-3 ctherm.ctherm3 7 6 = 7.0e-3 ctherm.ctherm4 6 5 = 9.0e-3 ctherm.ctherm5 5 4 = 1.1e-2 ctherm.ctherm6 4 3 = 4.0e-2 ctherm.ctherm7 3 2 = 3.0e-1 ctherm.ctherm8 2 tl = 1.5 rtherm.rtherm1 th 8 = 2.5e-1 rtherm.rtherm2 8 7 = 6.0e-1 rtherm.rtherm3 7 6 = 1.25 rtherm.rtherm4 6 5 = 8 rtherm.rtherm5 5 4 = 10 rtherm.rtherm6 4 3 = 43 rtherm.rtherm7 3 2 = 48 rtherm.rtherm8 2 tl = 50 }
RTHERM5
CTHERM5 4
RTHERM6 3
CTHERM6
RTHERM7 2
CTHERM7
RTHERM8
CTHERM8
tl
AMBIENT
TABLE 1. THERMAL MODELS COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.02 in2 4.0e-2 3.0e-1 1.5 43 48 50 0.05 in2 4.0e-2 3.5e-1 1.5 35 40 45 0.10 in2 4.2e-2 3.3e-1 1.5 35 37 42 0.25 in2 4.0e-2 3.0e-1 1.5 27 30 45 0.40 in2 4.0e-2 2.8e-1 1.5 27 29 37
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ITF87052SVT MO-193AA (TSOP-6)
6 LEAD JEDEC MO-193AA TSOP PLASTIC PACKAGE (SIMILAR TO SSOTTM-6)
A E E1 A 1
INCHES SYMBOL A A1 MIN 0.035 0.004 0.012 0.003 0.107 0.103 0.056 0.020 0.008 0.122 0.118 0.070 MAX 0.043
MILLIMETERS MIN 0.90 0.10 0.30 0.08 2.70 2.60 1.40 0.50 0.20 3.10 3.00 1.80 3 2 MAX 1.10 NOTES
6
e D b 4 3
b c D E
C
E1 e L
0.037 BSC 0.014 0.021
0.95 BSC 0.35 0.55 4
L 0o-8o 0.037 0.95
0.004in 0.10mm
0.039 1.00
0.075 1.90 0.024 0.60
0.095 2.40
NOTES: 1. All dimensions are within the allowable dimensions of Rev. B of JEDEC MO-193AA outline dated 10-99. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.006 inches (0.15mm) per side. 3. Dimension "E " does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.006 inches (0.15mm) per side. 4. "L" is the length of terminal for soldering. 5. Controlling dimension: Millimeter. 6. Revision 2 dated 5-00.
MO-193AA (TSOP-6)
8mm TAPE AND REEL
USER DIRECTION OF FEED 4.0mm 1.5mm DIAMETER HOLE 2.0mm C L 8.0mm 3.5mm 1.75mm
4.0mm COVER TAPE 13.0mm 13.0mm
178mm
60mm 9.0mm
GENERAL INFORMATION 1. 3000 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
SSOTTM-6 is a trademark of Fairchild Semiconductor.
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ITF87052SVT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369
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